定数定義

//12bitの2進数定義
12’b000011110000;

//4bitの10進数定義
4’d15;

分岐

always @( posedge pck ) begin
    if ( reset )
        {vga_r, vga_g, vga_b} <= 12'b000000000000;
    else if ( disp_enable ) begin        
        vga_r = 4'hA;
        vga_g = 4'd0;
        vga_b = 4'd0;
    end
    else
        {vga_r, vga_g, vga_b} <= 12'b000000000000;
end

Reference

http://www.icrus.org/machida/product/verilog.pdf
https://isle3hw.kuis.kyoto-u.ac.jp/